基于微处理器核的AAC解码软硬件协同优化

为了降低硬件成本和在较低频率下实现基于精简指令集计算机（reduced instruction set computer, RISC）处理器的先进音频编码（advanced audio coding，AAC），提出了一种软硬件协同优化策略，通过对解码关键子模块进行分析，从比特流解码、解码运算部分、播放控制3个方面来实现软件算法的优化，从而加快音频解码速度，减少存储空间，并根据优化结果对嵌入式RISC微处理器核进行配置.在现场可编程门阵列（field programmable gate array, FPGA）验证平台上实现了对128 kbps，44.1 kHz双声道AAC 低复杂度框架（low complexity profile, LC）的实时解码，运算量为25.51 MIPS，优化率为48.9%.

Hardware /software co-optimization of AAC decoder based on embedded microprocessor core

A hardware/software co-optimization strategy was proposed to reduce the hardware cost and implement a real-time advanced audio coding(AAC) decoder at lower frequency based on reduced instruction set computer(RISC) processor.Through setting up models for key sub-modules of decoding program,software algorithm including bit stream decoding,decoding algorithm and playing control strategy were optimized to speed up the audio decoding and reduce the memory.Based on the optimized software,an embedded microprocessor core was configured.A decoder on the field programmable gate array(FPGA) platform which required 25.51 MIPS to decode 128 kbps,44.1 kHz 2-channel AAC low complexity profile with temporal noise shaping in real-time was verified,and the optimization rate was 48.9%.