基于FPGA的HEVC后处理CNN硬件加速器研究

针对高效视频编解码标准中后处理CNN算法在通用平台运行时产生的高延时缺点，提出一种基于现场可编程逻辑门阵列（FPGA）的后处理卷积神经网络硬件并行架构。提出的并行架构通过改进输入与输出缓冲的数据并发过程，调整卷积模块整体并行度，加快模块硬件流水。实验结果表明，基于本文所提出的并行架构设计的CNN硬件加速器在Xilinx ZCU102上处理分辨率为176×144视频流，计算性能相当于每秒360.5 GFLOPS，计算速度可满足81.01 FPS，相比时钟频率4 GHz的Intel i7-4790K，计算速度加快了76.67倍,相比NVIDIA GeForce GTX 750Ti加速了32.50倍。在计算能效比方面，本文后处理CNN加速器功耗为12.095 J，能效比是Intel i7-4790K的512.90倍，是NVIDIA GeForce GTX 750Ti的125.78倍。

An FPGA-based HEVC post-processing CNN hardware accelerator

Aiming at the shortcomings of the post-processing CNN algorithm running on the common platform according to the high-efficiency video code standard, we propose a post processing convolutional neural network hardware parallel architecture based on field programmable gate array (FPGA) to improve the overall parallelism of the convolution module and the hardware flow of the module by optimizing the concurrent data input and output buffering process. Experiments on 176×144 video streams on the Xilinx ZCU102 show that the proposed CNN hardware accelerator can achieve an equivalent computational performance of 360.5G floating-point operation per second. The computation speed can satisfy 81.01 FPS, which is 76.67 times faster than that of the Intel i7-4790K with a clock frequency of 4Ghz. The speedup is 32.50 times faster than the NVIDIA GeForce GTX 750Ti. In the calculation of energy efficiency ratio, the proposal’s power consumption is 12.095W, 512.9 times of that of the Intel i7 4790K and 125.78 times that of the NVIDIA GeForce GTX 750Ti.