基于FPGA的HS400模式eMMC控制器设计与实现

介绍了eMMC及其在HS400高速数据传输模式下的工作原理，提出了一种eMMC控制器的设计方案。实现了200 MHz工作频率下，使用DDR传输模式进行数据传输的eMMC控制器，并通过CRC校验模块实现对传输数据的CRC校验，增强了系统的可靠性。实验平台采用母板/子板总体架构，在Xilinx Zynq 7000 FPGA开发板Zedboard上实现eMMC控制器，通过FMC接口与eMMC芯片子板进行通信传输。仿真及板级测试表明， HS400模式下数据读写 的传输速率最高可达400 MB/s，能够在实际的eMMC开发中有效提高eMMC设备的访问性能。

Design and implement of an eMMC controller in HS400 mode based on FPGA

We introduce the working principle of eMMC chip and its HS400 high speed data transmission mode, the design scheme of an eMMC controller, and the result of hardware verification. An eMMC controller that uses the DDR transmission mode for data transmission is implemented at a working frequency of 200 MHz, and the CRC verification module is employed to achieve the transmission data CRC checksum to enhance system reliability. The experimental platform adopts the motherboard/sub board architecture, and the eMMC controller is ultimately implemented on the Xilinx Zynq 7000 FPGA Zedboard development board to realize communication through the FMC interface and eMMC chip board. Simulation and board level tests show that data read and write operations in the HS400 mode can achieve a data transfer rate of up to 400 MB/s, which can effectively improve the access performance of the device during the actual eMMC development.