众核处理器的共享一级指令缓存研究

众核处理器设计在芯片面积上受到了巨大挑战,如何将有限的芯片面积投入到运算能力中,是众核处理器体系结构研究的热点。聚焦众核处理器的指令缓存结构设计,研究通过在多核核心之间共享一级指令缓存,以获取指令系统及处理器流水线性能的提升。给出了共享指令缓存的结构设计,对该结构进行了节拍级精确的性能模拟,并通过RTL级代码的综合得到了面积开销和时序指标。测试结果表明,共享指令缓存可以降低11%~27%的缓存脱靶率,提升4%~7%的流水线性能。

Shared L1 instruction cache for many core processors

Many core processor design faces a great challenge in terms of chip area utilization. How to improve the proportion of the computing units in the limited chip area is a hot topic in the research on many core architecture. We focus on the design of the instruction cache on the many core processor. The instruction cache is shared among several processing cores in order to improve the pipeline performance. We propose a design of shared instruction cache and implement cycle accurate performance simulation on it. The RTL codes of the shared instruction cache are synthesized to get the area cost and timing results. Experimental results demonstrate that the shared instruction cache can decrease 11% to 27% miss rate and improve the pipeline performance by 4% to 7%.