一种基于可重用激励发生机制的SoC验证平台

在系统芯片的设计中,传统的激励发生机制耗费人工多且难以重用,严重影响了仿真验证的效率。针对此问题,构建了一种基于可重用激励发生机制的虚拟SoC验证平台。该平台利用可重用的激励发生模块调用端口激励文件,仿真时将端口激励文件转换成对应于验证电路端口的时序信号。通过对通用同步/异步串行接收/发送器、中断及定时器等功能模块的验证,证明了激励发生机制具有较强的可观察性、可控制性及可重用性。验证结果分析表明,在验证不同的功能点时仅需修改固件及端口激励文件,使验证平台在重用时减少代码修改量,提高了灵活性和验证效率,缩短了系统芯片的验证时间。

A SoC verification platform based on reusable stimulus generation mechanism

Traditional stimulus generation mechanism is labor intensive and hard to reuse in the design process of system on a chip (SoC), thus the simulation efficiency is affected seriously. To solve this problem, we construct a virtual SoC verification platform based on the reusable stimulus generation mechanism. The verification platform calls a port stimulus file through a reusable stimulus generation module, and the stimulus file is converted into the timing signals that correspond to the ports of the verification circuit. The function verification of universal synchronous/asynchronous receiver/transmitter, interrupt and timer demonstrates the observability, controllability and feasibility of the stimulus generation mechanism. The verification result analysis shows that it only needs to modify the firmware and port stimulus files when different function points are to be verified. As a result, the amount of code changes during the reuse of the verification platform is reduced, the flexibility and efficiency are improved, and the SoC verification time is shortened.