基于CPLD的SDRAM控制器

高速数据采集卡设计中需要大容量的存储单元，静态存储器无法满足容量要求，故选用同步动态存储器(SI)RAM)为该数据采集系统的存储单元。通过VIIDL语言描述电路，设计了基于CPL，D的SDRAM控制器，从而简化了主机对SDRAM的读写及其相关操作。SDRAM控制器设计采用自顶向下模块化的设计方法，共分为四个模块：SDRAM控制器顶层模块、控制接口模块、命令模块和数据通路模块，SDRAM控制器顶层模块初始化并把其余三个模块有机地结合起来。测试结果证明设计的SDRAM控制器成功地实现了对SDRAM的读写操作，地址、数据、控制信号时序匹配，满足了系统设计要求。

SDRAM Controller Based on CPLD

Based on the demand of large capacity in high speed data acquisition system, SDRAM with large capacity is needed rather than the SRAM with small capacity. Using the VHDL as the circuit described language, the SDRAM Controller simplified the operation between the host and the SDRAM based on CPLD. Employing the top-to-bottom design method, the SDRAM Controller is divided into four modules: SDRAM control interface module, command module, data path module and controller top module which initialize and combine the other three modules. The tested results indicate that the SDRAM controller successfully operate the SDRAM with proper timing relation between address, data and control signal.