一种消除反馈延迟的全数字锁相环

针对传统数字锁相环存在的反馈滞后造成系统动、静态性能退化的问题,提出一种消除反馈滞后一拍的方法,以无反馈滞后理想数字锁相环为参考模型,利用数字锁相环当前输出与上一时刻输出,计算得到与理想数字锁相环一致的结果,从而消除反馈滞后一拍。所提出的锁相环仅以两个乘法器的额外开销即可大幅增强锁相环的稳定性,并且使在s域内设计的性能指标能够在z域内严格实现,克服了传统数字锁相环性能退化的问题。仿真和实验结果表明,所提改进的数字锁相环阶跃响应和频率特性均与理想数字锁相环一致,显著提高了锁相环性能,所提新算法增加的计算量较少,具有较大的实际应用价值。

An All-Digital Phase-Locked Loop with Compensating Feedback Unit Delay

The feedback unit delay in conventional digital PLL causes adverse effects to system steady-state and dynamic performance. Therefore, referred to ideal digital PLL without feedback delay, an improved digital PLL was proposed utilizing the present and previous outputs of PLL to calculate the ideal output. The proposed novel PLL with merely two additional multipliers can improve the system stability dramatically. Moreover, the performance indexes designed in s domain can be implemented strictly inz domain, to overcome the performance degeneration in conventional PLL. Simulation and experimental results show that both step response and frequency response of the novel digital PLL accord with those of the ideal digital PLL. The novel digital PLL improves the performance significantly with low computational burden, which implies its considerable practical value.