A High‐On/Off‐Ratio Floating‐Gate Memristor Array on a Flexible Substrate via CVD‐Grown Large‐Area 2D Layer Stacking |
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Authors: | Quoc An Vu Hyun Kim Van Luan Nguyen Ui Yeon Won Subash Adhikari Kunnyun Kim Young Hee Lee Woo Jong Yu |
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Affiliation: | 1. Center for Integrated Nanostructure Physics (CINAP), Institute for Basic Science (IBS), Suwon, Republic of Korea;2. Department of Energy Science, Sungkyunkwan University, Suwon, Republic of Korea;3. Department of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon, Republic of Korea;4. Korea Electronics Technology Institute, Seongnam, Republic of Korea |
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Abstract: | Memristors such as phase‐change memory and resistive memory have been proposed to emulate the synaptic activities in neuromorphic systems. However, the low reliability of these types of memories is their biggest challenge for commercialization. Here, a highly reliable memristor array using floating‐gate memory operated by two terminals (source and drain) using van der Waals layered materials is demonstrated. Centimeter‐scale samples (1.5 cm × 1.5 cm) of MoS2 as a channel and graphene as a trap layer grown by chemical vapor deposition (CVD) are used for array fabrication with Al2O3 as the tunneling barrier. With regard to the memory characteristics, 93% of the devices exhibit an on/off ratio of over 103 with an average ratio of 104. The high on/off ratio and reliable endurance in the devices allow stable 6‐level memory applications. The devices also exhibit excellent memory durability over 8000 cycles with a negligible shift in the threshold voltage and on‐current, which is a significant improvement over other types of memristors. In addition, the devices can be strained up to 1% by fabricating on a flexible substrate. This demonstration opens a practical route for next‐generation electronics with CVD‐grown van der Waals layered materials. |
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Keywords: | flexible memristors floating gates graphene heterostructures transition‐metal dichalcogenides |
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