FPGA-based digit-serial CSD FIR filter for image signal format conversion |
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| Affiliation: | 1. Lucent Technologies, 1247 S. Cedar Crest Blvd, #43C-308, Allentown, PA 18103, USA;2. Department of Electrical and Computer Engineering, 200 Union Street SE, University of Minnesota, Minneapolis, MN 55455, USA;1. School of Microelectronics, Xidian University, Xi''an, 710071, PR China;2. Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, Xi''an, 710071, PR China;1. State Key Laboratory Cultivation Base, Henan Province Key Laboratory of Gas Geology and Gas Control, Henan Polytechnic University, Jiaozuo 454003, China;2. Collaborative Innovation Center of Coal Safety Production of Henan Province, Jiaozuo 454003, China;3. Henan Province Key Laboratory of Biogenic Traces and Sedimentary Minerals, Henan Polytechnic University, Jiaozuo 454003, China;4. School of Resources and Safety Engineering, China University of Mining and Technology, Beijing 100083, China;1. Faculty of Pharmacy, The University of Sydney, NSW, Australia;2. NHMRC Center for Integrated Research and Understanding of Sleep (CIRUS), Woolcock Institute of Medical Research, The University of Sydney, NSW, Australia;3. Department of Respiratory and Sleep Medicine, Royal Prince Alfred Hospital, Camperdown, NSW, Australia;4. Faculty of Medicine, The University of Sydney, NSW, Australia |
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| Abstract: | This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs. |
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