Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study |
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| Affiliation: | 1. DIIN, University of Salerno, Italy;2. Department of Engineering and Computer Science and Mathematics, University of L''Aquila, Italy;1. Imec, Kapeldreef 75, 3001 Heverlee, Belgium;2. Micron Technology Belgium, Leuven, Belgium;3. SOITEC, Bernin, Crolles, France;4. SOITEC-USA, Austin, TX, USA;5. LSI/PSI/USP, University of Sao Paulo, Sao Paulo, Brazil;1. LTI Lab., University of Picardie Jules Verne, France;2. IMS Lab., University of Bordeaux, France;3. LIMMS/CNRS-IIS, Institute of Industrial Science, The University of Tokyo, Japan;1. UNESCO-UNISA Africa Chair in Nanosciences/Nanotechnology, College of Graduate Studies, University of South Africa, Muckleneuk ridge, PO Box 392, Pretoria, South Africa;2. University Sidi Mohamed Ben Abdellah, Faculty of Sciences Dhar el Mahraz, Laboratory of Solid state Physics, Group of Polymers and nanomaterials, PO Box 1796, Atlas, Fez 30 000, Morocco;3. Nanosciences African Network (NANOAFNET), iThemba LABS-National Research Foundation of South Africa, Old Faure Road, PO Box 722, Somerset West 7129, Western Cape Province, South Africa;4. Institut des materiaux Jean Rouxel de Nantes, 2, rue de la Houssinière Nantes, France |
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| Abstract: | A CMOS ring oscillator circuit is observed to operate even after a number of its FET's have undergone a hard gate oxide breakdown. The first breakdown is identified with emission microscopy and statistical tools to most likely occur in the circuit's nFET's. A physical model and an equivalent electrical circuit for an nFET after hard gate oxide breakdown are constructed and used to confirm the understanding of the impact of FET gate oxide breakdown on the ring oscillator. The observations are generalized to conclude that, provided stable soft breakdowns are the only gate oxide failures occurring at operating conditions, large parts of digital CMOS circuits will be unaffected by these failures. |
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