Improved structure for adiabatic CMOS circuits design

Two adiabatic circuits with complementary structure and operation are proposed in this paper. They employ two-phase sinusoidal power clock. The power consumption of the proposed circuits is comparable to that of some previously reported circuits. The problem of floating output nodes is solved by connecting two MOS transistors to the power clock. In particular, using the proposed architecture more than one stage of gates can be computed simultaneously within a single clock-phase, compared to only one stage is computed in every phase by most other adiabatic logic families. With this feature, the latency of the complex logic circuit is greatly improved and the number of buffers required for a pipelining circuit is also reduced. In this paper, a 2:1 multiplexer and full adder are illustrated and simulated. From the PSPICE simulation results, the effectiveness of the proposed approach and the low power characteristic of the designed circuits are validated.