Fast statistical delay evaluation of RC interconnect in the presence of process variations |
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| Li Jianwei, Dong Gang, Yang Yintang, Wang Zeng. Fast statistical delay evaluation of RC interconnect in the presence of process variations[J]. Journal of Semiconductors, 2010, 31(4): 045010. doi: 10.1088/1674-4926/31/4/045010 Li J W, Dong G, Yang Y T, Wang Z. Fast statistical delay evaluation of RC interconnect in the presence of process variations[J]. J. Semicond., 2010, 31(4): 045010. doi: 10.1088/1674-4926/31/4/045010.Export: BibTex EndNote |
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| Authors: | Li Jianwei Dong Gang Yang Yintang Wang Zeng |
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| Affiliation: | Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Microelectronics Institute, Xidian University, Xi'an 710071, China |
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| Abstract: | Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closed-form expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology. |
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| Keywords: | process variations RC delay static delay |
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