A high efficiency charge pump circuit for low power applications |
| |
Authors: | Feng Peng Li Yunlong Wu Nanjian |
| |
Affiliation: | State Key Laboratory for Super Lattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences,Beijing 100083,China |
| |
Abstract: | A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18 μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumping-stage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications. |
| |
Keywords: | high efficiency low power charge pump circuit high-voltage generator standard CMOS process |
本文献已被 万方数据 等数据库收录! |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |
|