A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems |
| |
Authors: | Salahddine Krit Hassan Qjidaa Imad El Affar Yafrah Khadija Ziani Messghati Yassir El-Ghzizal |
| |
Affiliation: | Faculty of Sciences Dhar El Mehraz, Laboratory of Electronic, Signal-Systymes and Informatic(LESSI)Fès, Morocco |
| |
Abstract: | This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs.This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption. |
| |
Keywords: | switch capacitor charge pump voltage doubler power consumption |
本文献已被 万方数据 等数据库收录! |