Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress |
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Authors: | Zhu Jing Qian Qinsong Sun Weifeng Liu Siyang |
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Affiliation: | National ASIC System Engineering Research Center,Southeast University,Nanjing 210096,China |
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Abstract: | The physical mechanisms triggering electrostatic discharge (ESD) in high voltage LDMOS power tran-sistors (> 160 V) under transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP) stress are investigated by TCAD simulations using a set of macroscopic physical models related to previous studies implemented in Sentaurus Device. Under VFTLP stress, it is observed that the triggering voltage of the high voltage LDMOS obvi-ously increases, which is a unique phenomenon compared with the low voltage ESD protection devices like NMOS and SCR. The relationship between the triggering voltage increase and the parasitic capacitances is also analyzed in detail. A compact equivalent circuit schematic is presented according to the investigated phenomena. An improved structure to alleviate this effect is also proposed and confirmed by the experiments. |
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Keywords: | electrostatic discharge transmission line pulsing very fast transmission line pulsing lateral doublediffused metal-oxide-semiconductor transistor |
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