A programmable systolic device for image processing based on mathematical morphology

Systolic array architectures are favourable for special purpose systems as they are simple and offer a high degree of concurrency. A programmable systolic device is designed to cater for all tasks of image processing based on mathematical morphology. The design consists of a systolic memory matrix accessible via a rotation operation by a linear systolic array of simple processing elements. The instruction set consists of 1-bit assignmments, logical and and or and shift operations on the memory. Thus extremely short clock cycles and a high degree of parallelism can be achieved.