一个电容阵列定制的100MS/s，9bit，0.43mW逐次逼近型模数转换器

本论文介绍了一个带定制电容阵列的低功耗9bit，100MS/s逐次比较型模数转换器。其电容阵列的基本电容单元是一个新型3D，电容值为1fF的MOM电容。除此之外，改进后的电容阵列结构和开关转换方式也降低了不少功耗。为了验证设计的有效性，该比较器在TSMC IP9M 65nm LP CMOS工艺下流片。测试结果如下：采样频率100MS/s，输入频率1MS/s时，有效位数（ENOB）为7.4,bit，信噪失真比（SNDR）为46.40dB，无杂散动态范围（SFDR）为62.31dB。整个芯片核面积为0.030mm2，在1.2V电源电压下功耗为0.43mW。该设计的品质因数（FOM）为23.75fJ/conv。

A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array

A low power 9 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits (ENOB) of 7.4 bit, a signal-to-noise plus distortion ratio (SNDR) of 46.40 dB and a spurious-free dynamic range (SFDR) of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm² and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit (FOM) of the SAR ADC achieves 23.75 fJ/conv.