一种基于55nmCMOS工艺，输出频率0.1G-1.5G Hz的低抖动锁相环

本文设计了一种0.1G-1.5GHz，3.07pS RMS 抖动的多相位输出锁相环。通过引入双路径电荷泵，极大的减小了锁相环中的低通滤波器的尺寸。基于指定的功耗约束，提出了一种新颖的压控振荡器、电荷泵与鉴频鉴相器的尺寸优化方法，使用该方法，每个模块输出相位噪声减小了约3-6dBc/Hz。该锁相环在55nm的工艺下流片，集成了16pF的MOM电容，占用面积仅为0.05平方毫米。输出1.5GHz信号时，功耗2.8mW，相位噪声为-102dBc/Hz@1MHz。

A 0.1-1.5 GHz, low jitter, area efficient PLL in 55-nm CMOS process

A 0.1-1.5 GHz, 3.07 pS root mean squares (RMS) jitter, area efficient phase locked loop (PLL) with multiphase clock outputs is presented in this paper. The size of capacitor in the low pass filter (LPF) is significantly decreased by implementing a dual path charge pump (CP) technique in this PLL. Subject to specified power consumption, a novel optimization method is introduced to optimize the transistor size in the voltage control oscillator (VCO), CP and phase/frequency detector (PFD) in order to minimize clock jitter. This method could improve 3-6 dBc/Hz phase noise. The proposed PLL has been fabricated in 55 nm CMOS process with an integrated 16 pF metal-oxide-metal (MOM) capacitor, occupies 0.05 mm² silicon area, the measured total power consumption is 2.8 mW @ 1.5 GHz and the phase noise is -102 dBc/Hz @ 1 MHz offset frequency.