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CAN总线与串行总线高速接口的设计
引用本文:朱开锐,罗雄文.CAN总线与串行总线高速接口的设计[J].探测与控制学报,2009,31(Z1).
作者姓名:朱开锐  罗雄文
作者单位:驻9804厂军事代表室,云南,曲靖,655000
摘    要:当前CAN总线与串口通信接口转换均采用单片机,有效转换速率很低,不能满足条件苛刻的场合;采用CPLD/FPGA进行协议直接转换的方案,能极大地提高系统的有效转换速率;为进一步提高系统的可靠性,采用CAN总线驱动器热冗余技术;通过CPLD/FPGA将CAN总线控制器的内部寄存器直接映像到PC104总线I/O上,解决了I/O映像或双口RAM速率较低、电路复杂的缺点.以RS485型串口为例,它的有效转换速率在同等情况下是传统产品的2~3倍,实时性和可靠性明显得到改善.

关 键 词:CAN总线  有效转换速率  热冗余

Design of High Speed CAN Bus and Serial Communication Interface
ZHU Kai-rui,LUO Xiong-wen.Design of High Speed CAN Bus and Serial Communication Interface[J].Journal of Detection & Control,2009,31(Z1).
Authors:ZHU Kai-rui  LUO Xiong-wen
Abstract:Singlechip was used in CAN bus and serial communication interface, whose valid transition speed is very low and can't satisfy rigorous demands. A new scheme, which used PC104 and CPLD/FPGA to transit directly, was put forward, and its interface circuits was simplified and can increase the valid transition speed greatly. In order to improve the reliability, CAN bus drivers hot redundancy technology was used. To solve low speed and complexity circuits by the way of I/O reflex or double-port RAM, interior registers in CAN bus controllers were mapped to I/O in PC104 bus directly by CPLD/FPGA. Taken RS485 as example, the valid transition speed is faster 2-3 times than traditional production, and the real-time and reliability are improved greatly.
Keywords:CPLD/FPGA  CAN Bus  CPLD/FPGA  valid transition speed  hot redundancy
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