New pulse mode neuro-fuzzy hardware architecture and application to image denoising

This paper focuses on a new digital architecture of pulse mode neuro-fuzzy system (PMNFS) with on-chip learning ability. The main purpose goal is to make use of the outstanding features of neuro-fuzzy in function approximation, and implement a reconfigurable architecture with on-chip learning on a field-programmable gate array (FPGA) platform. Details of the whole design with on-chip learning solutions are given. As an application illustrating the efficiency and scalability of the proposed PMNFS, we have considered the approximation of image denoising, which is a very important step in image processing. Experimental results show great efficiency of the proposed method, outperforming other denoising techniques. It was also demonstrated that such a system is strongly adaptive and gives good restored images independently of the kind of noises. Owing to learning, such feature cannot be met with conventional denoising techniques. Design synthesis results on a virtex II PRO FPGA platform are presented. Comparisons with conventional techniques as well as neural ones show higher performances of the designed PMNFS.