FPGA implementation of particle swarm optimization for Bayesian network learning |
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Authors: | Matthew J. Hibbard Eric R. Peskin Ferat Sahin |
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Affiliation: | 1. SRC, Inc., 6225 Running Ridge Road, North Syracuse, NY 13212, USA;2. Center for Health Informatics and Bioinformatics, New York University Langone Medical Center, 227 East 30th Street, #7-37, New York, NY 10016-8203, USA;3. Department of Electrical and Microelectronic Engineering, Kate Gleason College of Engineering, Rochester Institute of Technology, James E. Gleason Hall, 79 Lomb Memorial Drive, Rochester, NY 14623-5603, USA |
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Abstract: | Using a Bayesian network (BN) learned from data can aid in diagnosing and predicting failures within a system while achieving other capabilities such as the monitoring of a system. However, learning a BN requires computationally intensive processes. This makes BN learning a candidate for acceleration using reconfigurable hardware such as field-programmable gate arrays (FPGAs). We present a FPGA-based implementation of BN learning using particle-swarm optimization (PSO). This design thus occupies the intersection of three areas: reconfigurable computing, BN learning, and PSO. There is significant prior work in each of these three areas. Indeed, there are examples of prior work in each pair among the three. However, the present work is the first to study the combination of all three. As a baseline, we use a prior software implementation of BN learning using PSO. We compare this to our FPGA-based implementation to study trade-offs in terms of performance and cost. Both designs use a master–slave topology and floating-point calculations for the fitness function. The performance of the FPGA-based version is limited not by the fitness function, but rather by the construction of conditional probability tables (CPTs). The CPT construction only requires integer calculations. We exploit this difference by separating these two functions into separate clock domains. The FPGA-based solution achieves about 2.6 times the number of fitness evaluations per second per slave compared to the software implementation. |
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