A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-/spl mu/m CMOS process |
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| Authors: | Ohnakado T Yamakawa S Murakami T Furukawa A Nishikawa K Taniguchi E Ueda H Ono M Tomisawa J Yoneda Y Hashizume Y Sugahara K Suematsu N Oomori T |
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| Affiliation: | Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Hyogo, Japan; |
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| Abstract: | An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET. |
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