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一种数字CMOS工艺制造的10位100MS/s流水线ADC
引用本文:王睿,顾今龙,盛云,秦亚杰,洪志良.一种数字CMOS工艺制造的10位100MS/s流水线ADC[J].固体电子学研究与进展,2009,29(3).
作者姓名:王睿  顾今龙  盛云  秦亚杰  洪志良
作者单位:复旦大学专用集成电路与系统国家重点实验室,上海,201203
摘    要:介绍了采用0.18μm数字工艺制造、工作在3.3V下、10位100MS/s转换速率的流水线模数转换器。提出了一种适用于1.5位MDAC的新的金属电容结构,并且使用了高带宽低功耗运算放大器、对称自举开关和体切换的PMOS开关来提高电路性能。芯片已经通过流片验证,版图面积为1.35mm×0.99mm,功耗为175mW。14.7MS/s转换速率下测得的DNL和INL分别为0.2LSB和0.45LSB,100MS/s转换速率下测得的DNL和INL分别为1LSB和2.7LSB,SINAD为49.4dB,SFDR为66.8dB。

关 键 词:流水线模数转换器  数字工艺  金属叉指电容  对称自举开关  体切换开关

A 10 bit 100 MS/s Pipelined A/D Converter Implemented in Digital CMOS Process
WANG Rui,GU Jinlong,SHENG Yun,QIN Yajie,HONG Zhiliang.A 10 bit 100 MS/s Pipelined A/D Converter Implemented in Digital CMOS Process[J].Research & Progress of Solid State Electronics,2009,29(3).
Authors:WANG Rui  GU Jinlong  SHENG Yun  QIN Yajie  HONG Zhiliang
Abstract:A 3.3 V 10 bit 100 MS/s pipelined ADC in 0.18 μm digital CMOS process is presented.A new metal-finger capacitor structure for 1.5 bit MDAC is proposed.High bandwidth low power operational amplifiers(opamps),symmetrical bootstrapped switch and bulk-switching PMOS switch are employed in this ADC design to enhance circuit performance.The chip has been fabricated,occupying 1.35 mm×0.99 mm and consuming 175 mW.The measured differential nonlinearity(DNL)and integral nonlinearity(INL)are less than 0.2 LSB and 0.45 LSB,respectively at 14.7 MS/s and less than 1 LSB and 2.7 LSB,respectively at 100 MS/s.The signal-to-noise-and-distortion ratio(SNDR)and spurious-free-dynamic range(SFDR)are 49.4 dB and 66.8 dB,respectively for a full-scale input at 100 MS/s.
Keywords:pipelined ADC  digital CMOS process  metal-finger capacitors  symmetrical bootstrapped switch  bulk-switching PMOS switch
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