| 基于SystemVerilog的机载应答机验证技术的研究 |
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| 引用本文： | 田毅,李宏,马腾达,薛茜男. 基于SystemVerilog的机载应答机验证技术的研究[J]. 电子器件, 2013, 36(4): 535-539 |
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| 作者姓名： | 田毅 李宏 马腾达 薛茜男 |
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| 作者单位： | 中国民航大学适航审定技术与管理研究中心民用航空器适航与维修重点实验室;民用飞机模拟飞行国家重点实验室;中国民航大学航空自动化学院 |
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| 基金项目： | 国家自然科学基金项目(61179044);航空科学基金项目(20128067003);中国民航大学科研启动基金项目(2012QD26X) |
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| 摘 要： | 机载应答机对飞机安全有重大的影响,应当在功能仿真阶段模拟真实信号的脉冲宽度(含阈值)以对其中的可编程逻辑器件进行严格验证。首先研究引用标准正态分布随机生成脉冲宽度和间隔,并按照实际应用改进了正态分布算法。然后在对电子器件及IP核评估的基础上,通过SystemVerilog验证语言搭建验证平台,并使用改进后的算法生成验证激励。最后在某型应答机验证过程进行了应用,达到了高效、准确验证的目的。
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| 关 键 词： | 硬件 验证 正态分布 SystemVerilog |
Research of the Verification Technology for Airborne Transponder Based on SystemVerilog |
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| TIAN Yi,LI Hong,MA Tengda,XUE Qiannan. Research of the Verification Technology for Airborne Transponder Based on SystemVerilog[J]. Journal of Electron Devices, 2013, 36(4): 535-539 |
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| Authors: | TIAN Yi LI Hong MA Tengda XUE Qiannan |
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| Affiliation: | 1(1.Tianjin Key Laboratory for Civil Aircraft Airworthiness and Maintenance,Airworthiness Certification Technology Research and Management Center,Civil Aviation University of China,Tianjin 300300,China; 2.State Key Laboratory for Civil Aircraft Simulated Flight,Shanghai 200232,China; 3.Aeronautical Automation College,Civil Aviation University of China,Tianjin 300300,China) |
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| Abstract: | The airborne transponder has a major impact on the safety of aircraft. It should make a rigorous validation for the programmable logic device by real signal pulse width (including threshold value) simulation. Firstly, we studied standard normal distribution which is randomly generated pulse width and spacing, and then according to the practical application to improve normal distribution algorithm. Secondly, based on the assessment of electronic devices and IP core, SystemVerilog verification platformit is builed with validation incentive generated by improved algorithm. Finally, the efficient and accurate verification method is demonstrated in a certain type of transponder verification process. |
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| Keywords: | Hardware Verification Normal distribution SystemVerilog |
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