Design and Implementation of Open‐Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual‐Mode Operation

This paper proposes an open‐loop clock recovery circuit (CRC) using two high‐Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual‐mode operation. The DR filters are fabricated to obtain high Q‐values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak‐to‐peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo‐random binary sequence (PRBS) data with a word length of 2³¹?1 are less than 2.0 ps and 0.3 ps, respectively. The peak‐to‐peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error‐free operation of the 40 Gb/s‐class optical receiver with the dual‐mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.