| Abstract: | This letter presents a power efficient 64‐state Viterbi decoder (VD) employing a two‐stage radix‐4 add‐compare‐select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency‐division multiplexing (MB‐OFDM) ultra‐wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18‐μm CMOS technology. |
