ASIC设计中时钟偏移分析

目前的ASIC设计中,时钟偏移对同步数字电路的影响越来越大,它也越来越受到高速电路设计者的关注,因此如何解决它给电路带来的不利影响成了设计中的重要挑战.分析了时钟偏移的产生机理,提出了怎样使用CTS在时钟树中插入不同驱动能力的缓冲器,以平衡时钟网络,以及如何利用有用的时钟偏移来改善电路的时序.

Analysis of Clock Skew in ASIC Design

Clock skew becomes more and more important to synchronization circuits in current ASIC design, and it is an increasing concern for high-speed circuit designers. Therefore, it is a great challenge to reduce defect of clock skew in designs. In this paper, the generation principle of clock skew is analyzed. A method is proposed to balance the clock network by inserting diversified buffers in clock trees and the timing violation of the designs is fixed by using useful clock skew.