可重构电子系统芯片级在线自主容错方法研究

可重构电子系统芯片固定型故障的传统容错设计往往采用集中式控制方法,存在测试时间长、硬件资源利用率低、对外部控制器依赖性高等问题。因此,设计了一种具有分布式自主容错能力的可重构细胞阵列,通过将细胞内部查找表输出与参考值进行比较的方式进行循环检测,并利用冗余存储单元对故障查找表进行修复。以四位并行乘法器为例进行仿真验证,实验结果表明,新型可重构阵列的自主容错设计方法,比现有设计的硬件开销小,修复时间短,容错能力强,且设计复杂度不受阵列规模影响。

Research on chip-level autonomous on-line fault-tolerant method for reconfigurable electronic systems

The traditional fault-tolerant designs for reconfigurable electronic systems on-chip stuck-at fault mainly use the centralized control methods, which usually cause long testing time, low hardware resources utilization rate, and high dependence on external controller.To solve these problems, this paper designed a novel reconfigurable cell array with distributed autonomous fault-tolerant ability, each cell could implement cyclic self-detection by comparing LUTs' output with reference value, and used redundant storage unit to repair fault LUTs.Chose a 4 bits parallel multiplier as an example, the experiment result demonstrates that, compared with the existing design methods, this novel reconfigurable array has less hardware cost, shorter self-repair time, better fault-tolerance ability, and the design complexity isn't influenced by the array scale.