Digit-Serial Complex-Number Multipliers on FPGAs |
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Authors: | T. Sansaloni J. Valls K.K. Parhi |
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Affiliation: | (1) Dpto. Ing. Electrónica, Universidad Politécnica de Valencia, EPS Gandía, Ctra. Nazaret-Oliva sn, 46730 Grao de Gandía, Spain;(2) Broadcom Corporation, 16215 Alton Pkwy, Irvine, CA 92619, USA |
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Abstract: | This paper presents an optimized implementation on FPGA of digit-serial Complex-Number Multipliers (CMs) using Booth recoding techniques and tree adders based on Carry Save (CS) and Ripple Carry Adders (RCA). This kind of Complex-Number multipliers can be pipelined at the same level independent of the digit-size. Variable and fixed coefficient CMs have been considered. In the first case an efficient mapping of the modified Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5:3 and 4:3 converters in the CS structure and the utilization of RCA trees lead to a minimum area requirement. In the case of fixed coefficient CMs, partial products generator is based on look-up tables and multi-bit Booth recoding is used to reduce the area and increase the performance of the circuit. The study reveals that efficient mapping of the 5-bit Booth recoding to generate the partial products is the optimum multibit recoding when Xilinx FPGA devices are used. |
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Keywords: | complex-number multipliers digit-serial arithmetic Booth recoding FPGA |
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