| Abstract: | This paper discusses the design and performance of all-digital clock and data recovery mechanisms integrated in low-cost PLDs. Two designs have been explored and analyzed, using data sampling systems with phase detection and decision logic to select either the most appropriate sample as the recovered data or the most appropriate phase as the recovered clock. These mechanisms have been implemented in low cost PLDs from two major manufacturers. These PLDs have been further heavily loaded with typical communications functions, and the performance of the clock/data recovery circuits has been analyzed. The results show that different architectures behave differently, and that internal noise can significantly impair the performance of the circuit for high operating frequencies. This poses large difficulties to the re-usage of these blocks as generic virtual components. Nevertheless their overall performance typically exceeds regular telecommunications requirements.Rui L. Aguiar concluded his Licenciatura, M.Sc. and his PhD at the University of Aveiro, Portugal, in the years of 1990, 1995 and 2001 respectively. He is currently a professor at the Universidade de Aveiro and a researcher at Instituto de Telecomunicações. He has published over 100 papers in national and international Journals and conferences in electronics and telecommunications systems and networks. He has been involved in several national and European projects and has been active in the technical committee of several conferences. His current main interests lie in communication circuits and systems, focusing especially in high complexity and strict timings problems.Mónica Figueiredo received the Licenciatura degree in Electrical Engineering from University of Coimbra, Portugal, and the M.Sc. degree in Electronics and Telecommunications Engineering from University of Aveiro, Portugal, in 1999 and 2003, respectively. Since 1999, she is an Assistant Lecturer in the Department of Electrical Engineering, Instituto Politécnico de Leiria, Portugal and a researcher at Instituto de Telecomunicações. Her research interests include PLL, DLL and synchronization systems. |
