A 34-ns 16-Mb DRAM with controllable voltage down-converter |
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| Authors: | Hidaka H. Arimoto K. Hirayama K. Hayashikoshi M. Asakura M. Tsukude M. Oishi T. Kawai S. Suma K. Konishi Y. Tanaka K. Wakamiya W. Ohno Y. Fujishima K. |
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| Affiliation: | Mitsubishi Electr. Corp., Hyogo, Japan; |
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| Abstract: | A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity.<> |
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