Clock gating methodologies and tools: a survey

Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Copyright © 2015 John Wiley & Sons, Ltd.