An all‐digital DLL with duty‐cycle correction using reusable TDC

This paper presents the design of an all‐digital delay‐locked loop (ADDLL) with duty‐cycle correction using reusable time‐to‐digital converter (TDC). The proposed ADDLL uses a reusable TDC for achieving a wide‐operating frequency range. In addition, it achieves the frequency doubling output clock easily by changing the quantization interval. It is implemented in a 0.18‐µm complementary metal‐oxide semiconductor technology. This circuit corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The output duty cycle is corrected to 50 ± 1.5% as the input duty cycle ranges from 25% to 75%. The acceptable input frequency range is from 300 to 900 MHz without frequency doubling. The acceptable input frequency range is from 150 to 450 MHz when using frequency doubling. It dissipates 6.2 mW from a 1.8‐V supply at 900 MHz. The peak‐to‐peak and RMS jitters at 900 MHz are 14 and 1.8 ps, respectively. Copyright © 2015 John Wiley & Sons, Ltd.