基于VerilogHDL语言的DPLL的数控振荡器设计

随着通讯技术、集成电路技术的飞速发展和系统芯片(SoC)的深入研究,数字锁相环技术应用越来越广泛.数字锁相环数控振荡器设计是数字锁相环电路的关键部分,在利用Verilog语言配合Xilinx的FPGA的基础上,采用两种方法实现数控振荡电路.一种是根据脉冲加/减电路编写RTL代码实现;另一种是采用有限状态机编写RTL代码实现.并使用综合软件Synplify7.5对两种满足设计要求的RTL代码进行综合分析.

Design of NCO of DPLL based on VerilogHDL

With the fast development of communication technology, digital integrated circuit and SoC, DPLL technology will be used widely. The Numerically Controlled Oscillator is the key component it the implementation of DPLL. Two methods were adopted to achieve NCO based on the combination of Verilog language and FPGA of Xilinx. One is implemented by writing RTL codes based on pulse plus/minus circuit; the other is implemented by finite state machine. The comprehensive analyses of these two RTL codes were made with the help of Synplify7.5.