Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-${mu}hbox{m}$ 3.3-V CMOS Technology

A 5.0/3.3/1.8-V tolerant I/O buffer implemented using typical CMOS 2P4M 0.35-mum process is proposed in this paper. Unlike traditional mixed-voltage-tolerant I/O buffers, the proposed I/O buffer can transmit and receive signals with voltage levels of 5.0/3.3/1.8 V. By using a stacked PMOS and a stacked NMOS at the output stage and a dynamic gate bias generator providing appropriate control voltages for the gates of the stacked PMOS, gate-oxide overstress and hot-carrier degradation are avoided. Moreover, gate-tracking and floating n-well circuits are used to remove undesirable leakage current paths. The proposed topology can be applied to any technologies with the constraint of VDD < VDDH < 2 times, which should be considered carefully in sub-100-nm technologies. Measurement results on silicon verify the function and the gate-oxide reliability of the proposed I/O buffer. The maximum transmitting speed of the proposed I/O buffer is measured to be 80/120/84 Mb/s for the supply voltage of I/O buffer at 5.0/3.3/1.8 V, respectively, given the load of 29 pF.