基于FPGA的DDR存储器突发读取设计技术

针对大规模采集数据读取时间较长的问题，特别是PCI总线接口的微处理器，采用单周期读取方式时，将会严重影响采集数据的实时处理。通过在FPGA中设计PCI接口控制器和DDR控制器，将PCI总线接口协议转换到内部自定义局部总线，采用双端口FIFO 作为时序同步控制缓冲器，同步内部局部总线和DDR控制器，从而解决了微处理器对DDR存储器突发读取的时序同步问题，实现了大规模采集数据的快速上传。

Design technology of burst reading to DDR memory based on FPGA

The reading of large scale acquiring data will consume long time. Especially, while single period to read data is chosen, microprocessor interface of PCI bus will influence real time dealing of acquiring data seriously. In this paper, PCI interface controller and DDR controller is designed in FPGA and the protocol of PCI bus transformed to user defined local bus of interior. The double interface FIFO is taken as the control buffer of clock synchronization, which used to synchrony local bus of interior and DDR controller. Thereby, the problem of clock synchronization is solved between microprocessor and DDR memory and the rapid uploading of large scale acquiring data is realized.