一种面向流应用加速的可重构协处理器

以图形处理、数字信号处理等为代表的流应用,对微处理器提出了高并行度、高性能和高带宽的要求。针对流应用加速的流处理器体系架构得到了广泛研究。流体系结构大多集成大量的功能单元、开发多层次并行和存储来加速流应用,但同时增加了系统功耗和芯片面积。分析和比较了近年来主流的流处理器架构,提出了一种用于流应用加速的可重构协处理器。该协处理器针对流应用特点,实现了数据级和指令级并行,并集成了多个可以动态配置的运算单元,可动态配置其运算类型和数据类型,提升系统灵活性,降低芯片面积。针对典型算法,该处理器实现了更高的加速比,综合后延时为9.74 ns,功耗为63.69 mW。

A Reconfigurable Coprocessor for Streaming Applications

Streaming applications present high performance and large bandwidth requirements to microprocessors. Stream architectures have been got wide research attention for the performance improvement of streaming applications. However, the power consumption and chip area are increased by the increasing number of functional units. A reconfigurable coprocessor for streaming acceleration was proposed. The coprocessor exploited the data and instruction level parallelism, and integrated several reconfigurable multi-operation arithmetic units for system flexibility. The proposed coprocessor achieved higher performance. The delay of the coprocessor was 9.74 ns and the power consumption was 63.69 mW.