针对逻辑门功能异常的VLSI故障仿真方法研究

为准确评价测试集对超大规模集成电路（VLSI）内部故障的覆盖效果，提出一种VLSI故障建模与仿真方法。首先，在电路级综合运用仿真和实验手段向逻辑门内部注入多个故障，统计并分析这些故障对其功能的影响以构建由变异真值表（MTT）组成的故障字典；其次，考虑MTT及其发生的相对概率权重，提出一种有效的测试覆盖率评价模型，并将其应用于门级故障仿真算法中；最后，针对若干组合逻辑基准电路进行了实例验证，仿真实验结果表明，所提方法相较于经典的固定值故障模型能够更真实地反映测试集的故障覆盖能力。

Fault simulation of VLSI based on functional fails of logic gate

In order to evaluate the fault coverage in VLSI accurately, a new logic fault modeling and simulation method is proposed in this paper. Firstly, the circuit level faults are injected into the logic cells by simulation and experiments, and the fault dictionary consisted of MTTs is built by analyzing the experimental data. Secondly, an effective testing coverage model is proposed based on the MTTs and their weights, which are then applied to the gate level fault simulation. At Last, the proposed method is proved on several combinational benchmark circuits. The results show that, comparing to the traditional stack at fault model, the proposed method can better reflect the fault coverage capability of a given testing set.