Differential bidirectional transceiver for on-chip long wires

This work presents a differential bidirectional transceiver (DBT) for on-chip long wires. To enhance operating speed and reduce power consumption, the voltage swing on the wire is reduced using current-mode scheme. Consequently, our design performs higher data rate when wire length is extended. Moreover, adoption of differential scheme with a moderate tradeoff of area effectively lowers power supply noise and common mode noise. The receiver adopts four input differential pairs along with current summation circuit to evaluate small signal differences of every that state resulted from transmitting different data. Simulations using 0.18-μm device model indicates that the total input to output delay over a 5 mm long wire is 0.96 ns, with a power consumption of 8.724 mW at a speed of 1.2 Gbps and a maximum achievable data rate of 1.5 Gbps. A test chip is realized and successfully verifies the performance of the transceiver.