Tunable Crystal Nanostructures of Pentacene Thin Films on Gate Dielectrics Possessing Surface‐Order Control

To enhance the electrical performance of pentacene‐based field‐effect transistors (FETs) by tuning the surface‐induced ordering of pentacene crystals, we controlled the physical interactions at the semiconductor/gate dielectric (SiO₂) interface by inserting a hydrophobic self‐assembled monolayer (SAM, CH₃‐terminal) of organoalkyl‐silanes with an alkyl chain length of C8, C12, C16, or C18, as a complementary interlayer. We found that, depending on the physical structure of the dielectric surfaces, which was found to depend on the alkyl chain length of the SAM (ordered for C18 and disordered for C8), the pentacene nano‐layers in contact with the SAM could adopt two competing crystalline phases—a “thin‐film phase” and “bulk phase” – which affected the π‐conjugated nanostructures in the ultrathin and subsequently thick films. The field‐effect mobilities of the FET devices varied by more than a factor of 3 depending on the alkyl chain length of the SAM, reaching values as high as 0.6 cm² V^?1 s^?1 for the disordered SAM‐treated SiO₂ gate‐dielectric. This remarkable change in device performance can be explained by the production of well π‐conjugated and large crystal grains in the pentacene nanolayers formed on a disordered SAM surface. The enhanced electrical properties observed for systems with disordered SAMs can be attributed to the surfaces of these SAMs having fewer nucleation sites and a higher lateral diffusion rate of the first seeding pentacene molecules on the dielectric surfaces, due to the disordered and more mobile surface state of the short alkyl SAM.