New CMOS circuit implementation of a one-bit full-adder cell

A new mirror CMOS circuit implementation of a one-bit full-adder cell is proposed. Using CMOS technology provides zero static power consumption and the freedom from fractional voltage levels at the internal nodes (no voltage recovery is needed). The solution proposed is shown to be superior in carry speed to any alternative CMOS implementation reported so far, and should therefore be suitable for building high-speed multibit adders.