Elimination of poly-Si gate depletion for sub-65-nm CMOS technologies by excimer laser annealing |
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| Authors: | Hiu Yung Wong Takeuchi H Tsu-Jae King Ameen M Agarwal A |
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| Affiliation: | Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA; |
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| Abstract: | Pulsed excimer laser annealing (ELA) is used to reduce the poly-Si gate depletion effect (to <0.1 nm). Low resistivity (0.58 m/spl Omega//spl middot/cm) and high active boron concentration (4/spl times/10/sup 20/ cm/sup -3/) at the gate-oxide interface are achieved while preserving the gate oxide quality and avoiding boron penetration, to meet International Technology Roadmap for Semiconductors requirements for sub-65-nm CMOS technology nodes. ELA is compatible with high-/spl kappa/ dielectric (HfO/sub 2/) and results in significantly lower gate leakage current density as compared with rapid thermal annealing (RTA). |
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