| 基于FPGA的Turbo译码交织器设计 |
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| 引用本文： | 赵旦峰,雷李云,罗清华.基于FPGA的Turbo译码交织器设计[J].太赫兹科学与电子信息学报,2007,5(3):186-189. |
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| 作者姓名： | 赵旦峰 雷李云 罗清华 |
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| 作者单位： | 哈尔滨工程大学,信息与通信工程学院,黑龙江,哈尔滨,150001 |
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| 摘 要： | 介绍了一种Turbo译码交织器的现场可编程门阵列（Field Programmable Gate Array，FPGA）硬件实现方案，将交织算法的软件编程和FPGA内部的硬件存储块相结合，有效地降低了译码器的硬件实现复杂度，减小了译码延时，并且给出了具体的译码器内交织器FPGA实现原理框图。
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| 关 键 词： | Turbo码 交织器 译码 延时 |
| 文章编号： | 1672-2892（2007）03-0186-04 |
| 修稿时间： | 2006-12-262007-03-16 |
Design of Turbo Decoder Interleaver Based on FPGA |
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| ZHAO Dan-feng,LEI Li-yun,LUO Qing-hua.Design of Turbo Decoder Interleaver Based on FPGA[J].Journal of Terahertz Science and Electronic Information Technology,2007,5(3):186-189. |
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| Authors: | ZHAO Dan-feng LEI Li-yun LUO Qing-hua |
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| Affiliation: | School of Information and Communication Engineering, Harbin Engineering University, Harbin Heilongjiang 150001, China |
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| Abstract: | This paper has introduced a FPGA implementation scheme of interleaver of turbo decoder. This scheme, which combines software programme of interleaver algorithm with the block memory of FPGA, effectively reduces the implementation complexity of the decoder, and the delay of decoding, and shows a detailed FPGA implementation schematic diagram. |
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| Keywords: | FPGA |
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