A floating well method for exact capacitance-voltage measurement of nano technology |
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| Authors: | Hung-Der Su Bi-Shiou Chiou Shien-Yang Wu Ming-Hsung Chang Kuo-Hua Lee Yung-Shun Chen Chih-Ping Chao Yee-Chaung See Sun JY-C |
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| Affiliation: | Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan; |
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| Abstract: | Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology. |
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