The Impact of Oxide Traps Induced by SOI Thickness on Reliability of Fully Silicide Metal-Gate Strained SOI MOSFET

In this letter, we investigate the effects of oxide traps induced by various silicon-on-insulator (SOI) thicknesses $({T}_{rm SOI})$ on the performance and reliability of a strained SOI MOSFET with SiN-capped contact etch stop layer (CESL). Compared to the thicker ${T}_{rm SOI}$ device, the thinner ${T}_{rm SOI}$ device with high-strain CESL possesses a higher interface trap $({N}_{rm it})$ density, leading to degradation in the device performance. On the other hand, however, the thicker ${T}_{rm SOI}$ device reveals inferior gate oxide reliability. From low-frequency noise analysis, we found that thicker ${T}_{rm SOI}$ has a higher bulk oxide trap $({N}_{rm BOT})$ density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior TDDB reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker ${T}_{rm SOI}$ devices in this strain technology.