高性能RISC微处理器硬件仿真器设计

在微处理器设计中，为了系统级软硬件协同仿真，在后端设计前必须采用硬件仿真器对设计进行系统验证．为此，采用FPGA设计32位RISC流水线结构微处理器的硬件仿真器．此设计主要包括以下特点：采用内存管理单元(MMU)可以实现虚拟地址管理；包括片上Cache，其中包括指令Cache(I-Cache)和数据Cache(D-Cache)；采用标准SYSAD接口设计；包括片上乘除处理单元(MDU)；实现精确异常处理．设计采用XILINX公司的xc2v2000实现，其工作频率为30MHz．

High Performance RISC Microprocessor Hardware Simulator Design

During the microprocessor design, in order to do the software/hardware co-simulation, the hardware simulator of the microprocessor must be designed before the back-end design of the chip. The hardware simulator of a 32-bit RISC pipeline microprocessor, which is implemented with FPGA, is provided in this paper. Its primary features include: on-chip memory manage unit (MMU), which is used to realize virtual memory management; on-chip primary cache, which includes instruction cache and data cache; standard SYSAD system interface; on-chip multiply/divide unit (MDU); precise exception handling. The hardware simulator is implemented with the FPGA xc2v2000 of the XILINX company and its work clock frequency is 30MHz.