Minimization of Data Address Computation Overhead in DSP Programs |
| |
Authors: | Bernhard Wess |
| |
Affiliation: | (1) Institut F. Nachrichtentechnik u. Hochfrequenztechnik, Vienna University of Technology, Austria |
| |
Abstract: | Modern digital signal processors (DSPs) provide dedicated address generation units (AGUs) which support data memory access
by indirect addressing with automatic address modification in parallel to other machine operations. There is no address computation
overhead if the next address is within the auto-modify range. Typically, optimization of data memory layout and address register
assignment allows to reduce both execution time and code size of DSP programs. In this paper, we present an optimization technique
for integrated data memory layout generation and address register assignment. We use a generic AGU model which captures important
addressing capabilities of DSPs such as linear addressing, modulo addressing, auto-modifying, and indexing within a given
auto-modify range. Experimental results demonstrate that the proposed technique significantly outperforms existing optimization
strategies.
This revised version was published online in July 2006 with corrections to the Cover Date. |
| |
Keywords: | Digital signal processors data memory layout address register assignment |
本文献已被 SpringerLink 等数据库收录! |
|