| 基于CPLD的HDB3编译码器 |
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| 引用本文： | 贾惠彬,王兰勋.基于CPLD的HDB3编译码器[J].电子科技,2005(9):37-40. |
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| 作者姓名： | 贾惠彬 王兰勋 |
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| 作者单位： | 河北大学,电子信息工程学院,河北,保定,071002;河北大学,电子信息工程学院,河北,保定,071002 |
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| 摘 要： | 通过对HDB3编译码原理的分析,提出了一种基于可编程逻辑器件EPM7064SLC44和模拟开关4052实现HDB3编译码的方法,给出了硬件设计电路图、软件设计流程和HDB3编译码器的仿真波形.此实现方法具有硬件设计简单、运行速度快、成本低等优点.同时由于CPLD可重复编程的特点,可以对它进行在线修改,便于设备的调试和运行.此编译码器已经过实际测试,运行稳定可靠,可用于实际电路中.
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| 关 键 词： | HDB3码 CPLD Verilog语言 |
| 收稿时间： | 2005-03-28 |
| 修稿时间： | 2005年3月28日 |
HDB3 Encoder and Decoder Based on CPLD |
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| Jia Huibin,Wang Lanxun.HDB3 Encoder and Decoder Based on CPLD[J].Electronic Science and Technology,2005(9):37-40. |
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| Authors: | Jia Huibin Wang Lanxun |
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| Abstract: | By analyzing the principle of HDB3 encoding and decoding, this paper gives a novel HDB3 encoding method based on EPM7064slc44 and analogy switch 4052, and presents the circuit diagram of hardware design, the flow of software design and the simulated waveform of HDB3 encoder and decoder. The method has the advantages of simple hardware design, high speed and low cost. In addition, since CPLD can be reprogrammed, it can be repaired online, thus making it convenient to debug and run the equipment. Testing shows that this encoder and decoder has stable performance and therefore can be applied to circuitry. |
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| Keywords: | CPLD |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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