基于组合逻辑最小化技术的时序逻辑综合方法

介绍一种以组合逻辑最小化工具为基础，提出按满足压缩状态表约束关系进行状态分配的新思想，通过一系列的转换，可完成从描述时序逻辑的原始状态表到满足该状态表状态转换要求的由ＰＬＡ作为组合逻辑部件的时序逻辑电路的转换。由于该时序逻辑综合新方法在处理过程中要涉及解大型覆盖表的问题，为此提出满足压缩状态表约束关系的状态分配的简化算法。文中用一些实例说明简化算法的具体运算过程。结果表明简化算法可导出满足原始状态表的较简化的时序逻辑表达式。

A NEW METHOD OF SEQUENTIAL LOGIC SYNIHESIS BASED ON COMBINATIONAL LOGIC MINIMIZATION

This paper introduces a new method which is different from classical sequential logic synthesis. This method, based on combinational logic minimization, proposes a new idea to proceed state assignment according to constrained.relation of compressed state table. After a series of transformations, it can implement the transformation from the primitive state table to sequential logic circuits which uses PLA as a combinational logic unit. Because this new method must solve a large scale covering table, this paper proposes a simplified algorithm This paper also proposes some practical examples to show the calculation processes of the simplified algorithm. The results demostrate that this simplified algorithm can drive the simpler sequential logic expression which is implemented from the primitive state table.