系统级CMOS电路的低功耗设计

随着集成电路规模的增大和工作频率的提高，功耗已经成为面积和性能之外的主要设计目标。低功耗设计可以在不同的设计层次进行考虑，早期的设计确定了系统的构架，对功耗的影响最大，因此本文重点探讨了RTL级和系统级的低功耗设计，具体的途径有：实行有效的功耗管理；采用并行处理和流水线结构；采用分布式的数据处理结构以及用专用电路代替可编程处理器。

System Level Low Power Design in CMOS Circuit

As the steady growth of chip scale and operating frequency, power was regarded as one of the top concerns in VLSI digital system. In this paper, the mechanisms for power dissipation in CMOS digital circuits are described. The main methodologies for low power are discussed. There are three recurring themes in low-power design. Firstly,avoid waste. Secondly, trade area and performance into power and lastly, careful partition in order to process data signal locally. It should be known that RTL architecture and system - level optimizations offer the greatest opportunities for power reduction. A number of specific low power techniques for abstraction of system level are discussed in detail. In these levels,techniques model the impact of concurrency,power management,locality,and data representing are described.